1. Field of the Invention
The invention relates to integrated circuit memories and, more specifically, to a method and apparatus for testing multiple random access memory (RAM) blocks.
2. Art Background
Random access memories (RAM) are common devices used in computers and many other digital systems. When a monolithic RAM is fabricated, errors in the fabrication process may render elements of the RAM defective. To avoid accessing the defective elements of the RAM, the defective elements are located and bypassed. The defective elements are located by a testing technique that reads and writes data to each memory cell (one bit) in the RAM to determine whether the particular cell is functioning properly.
In an integrated cache memory device as disclosed in a related application, "Integrated Cache Memory," filed Dec. 8, 1994, Ser. No. 08/351,900, a cache RAM is divided into two elements, a data RAM and a TAG RAM, and each element must be thoroughly tested. A data RAM stores data that it transfers to a central processing unit (CPU) or a storage device such as a disk drive. A TAG RAM stores higher order addresses. When the contents of the internal TAG RAM are equal to the higher order address of an accessed memory cell, the data RAM is enabled to access the data bus. The TAG RAM is provided the addresses that it stores by a controller internal to the RAM memory and the TAG RAM provides data only to the data RAM and controller in a normal mode of operation. Thus, as previously stated, in normal mode, the TAG RAM does not provide data to any devices external to the RAM memory or receive data to be written from any external devices. In test mode, however, the TAG RAM must be accessed so that it may be tested and repaired.
Since the TAG RAM must be tested, lines must be added to the memory to allow the TAG RAM to interface with a testing device. If there are N blocks of TAG RAM corresponding to N blocks of data RAM, and each TAG RAM has 20 tag bits that need to be interfaced with the testing device, 2 * 20 * N lines would need to be added to the memory solely for purposes of testing the TAG RAM. The factor of 2 arises because separate lines must be added for read and write operations since a TAG RAM, unlike a data RAM, requires separate interfaces for read and write operations. These additional lines occupy a relatively large amount of chip area because the lines must couple the TAG RAM with an I/O strucutre that interfaces with the testing device and the I/O structure is typically located relatively far from the TAG RAM. Thus, the lines required for testing the TAG RAM greatly increase the size of the RAM.
As will be described, the present invention overcomes the limitations of the prior art by providing a method and apparatus for testing multiple blocks of TAG RAM with only a modest increase in the size of the RAM.